1. Field of the Invention
The present invention generally relates to the field of integrated circuits. In particular, the present invention is directed to an I/O circuit power routing system and method.
2. Background of the Invention
Thus far, the semiconductor industry has succeeded in pushing forward the famous Moore's law on technology scaling. This continuous push results in future very large scale integration (VLSI) designs characterized by higher integration densities, higher operating frequencies, and reduced feature size. Reduced feature size leads to higher sheet resistivity for the metal wires that connect electrical devices to their corresponding electrical networks. Higher operating frequencies result in an increase in the dynamic power dissipated by the chips. Higher integration densities increase the number of transistors on the chip and accordingly increase the chip power dissipation.
Furthermore, leakage power, also referred to as static power, is increasing significantly from one technology to the next. In an attempt to address the increased power dissipation, as well as address other reliability requirements such as oxide breakdown voltage, the supply voltage is reduced in newer technologies. This reduces the noise margins and makes the designs more sensitive to voltage drops, also known as IR drops. While excessive voltage drops may cause functional failures, less severe voltage drops increase gate delays, which affect chip timing and make it harder to meet a chip's timing requirements.
The trend of increased power dissipation, lower supply voltage, and smaller feature size leads to higher current densities flowing in the power distribution networks of modem VLSI chips. Higher current densities and reduced sheet resistivity raise the chip susceptibility to reliability concerns, such as electromigration (EM) and electrostatic discharge (ESD), both of which can cause physical damage and chip failure.
Presently, a large number of chips are made using designs in which the input/output (I/O) circuits can be placed essentially anywhere on the chip and are not limited to the periphery of the chip. This type of chip is often referred to as a “flip chip.” An important aspect of the physical design of flip chips relative to I/O circuits is the sizing and routing of the wiring that connects the I/O circuits to the appropriate on-chip power distribution networks. “Power routing” of I/O circuits is the process of connecting the power service terminals (PSTs) of every I/O circuit (i.e., I/O pins where power is supplied to the I/O circuit) to the power distribution network. The metal wires connecting the I/O PSTs to the power distribution network are referred to as “power routes.” By controlling the widths of the I/O power routes, the effective resistance of the power routes, as well as the current densities in those routes, can be controlled to satisfy the electrical requirements of the design. The process of modifying the widths of the power distribution wires, also referred to as “wire sizing,” has been discussed in the literature to satisfy EM reliability requirements of generic power mesh structures.
For I/O circuits to function properly and meet their specifications, a set of electrical constraints, defined by either the technology developers or the chip designers, needs to be satisfied. A subset of these constraints related to the power routes of the I/O circuits are checked by the IR, EM, and ESD constraints.
IR checks: Supply currents flowing through metal conductors cause voltage drops across the conductors. Consequently, the voltage at the circuit pins is less than the voltage applied at the module pins. The IR drop checks are defined to guarantee that the voltage drops at the PSTs of the I/O circuits are less than a specified percentage of the supply voltage. This guarantees that the I/O circuits meet their performance specifications, which strongly depend on the value of the voltage at the PSTs of the I/O circuits.
EM checks: Electromigration is an important reliability failure mechanism that is becoming a more serious concern in shrinking technologies. Electromigration is defined as the mass transport of metal ions due to the momentum exchange between the metal ions and the moving electrons that represent the electric current flowing through the metal wires. A direct current in a metal wire running for a substantial period of time eventually causes the formation of voids or hillocks. In circuit terms, a void formation means an open circuit in the wire and a hillock formation means that the wire gets shorted to other wires. Either scenario may cause chip failure. For each technology, the technology developers define maximum EM current density limits as a function of the chip lifetime and temperature. It is then the designer's responsibility to make sure that current densities flowing through the metal wires on the chip are less than the specified technology limits. This is basically what defines the EM checks.
ESD checks: Electrostatic discharge is another important reliability failure mechanism that chip designers need to take into consideration. An ESD event is defined as the transfer of charge between bodies of different electrostatic potential in proximity or through direct contact. There are three different ESD models recognized in the semiconductor industry: (1) human body model; (2) machine model; and (3) charged device model. The difference between these models is the definition of their criteria in terms of how much charge can be injected into the system without damaging chip circuitry. To protect the chip circuitry against an ESD event, ESD clamps are utilized to help conduct a discharge path to the ground network. An ESD clamp is effectively a huge transistor (or diode) that is turned off except in the presence of an ESD event. In the case of an ESD event, the clamp turns on, creating a path for the charge to be drained into the ground network, thus, allowing the safe discharge of the ESD event while avoiding damage to chip circuitry. The ESD check is usually defined in terms of a maximum limit on the effective resistance of the power distribution network (including the power routes) from every I/O circuit to the ESD clamps.
The continual push for high performance and low power designs in current and future technologies makes it more difficult to meet the different electrical requirements of the designs, such as satisfying the IR drop, EM, and ESD electrical requirements. As mentioned, the widths of the power routes of the I/O circuits can be controlled to guarantee the satisfaction of all the electrical constraints. However, the processes of power routing and electrical analysis are typically independent. Most existing techniques rely on generic guidelines for power routing the I/O circuits. These guidelines are usually manually developed by experienced engineers relying on their knowledge of typical operation of I/O circuits and the design of the on-chip power distribution. Such guidelines are usually not I/O instance-specific and they do not necessarily guarantee the satisfaction of the electrical constraints for all I/O circuits. On the other hand, analysis tools have been developed to check for and capture the electrical violations in a design. Such tools utilize techniques that extract and simulate the power distribution networks excited by the different I/O circuits.
Consequently, a major drawback of existing design techniques is that the power routing design step is invoked independently of the electrical analysis design step. Thus, any violations reported by the electrical analysis step are then fixed manually by the designers. This is usually a tedious process that requires a number of iterations that may result in schedule delays. With newer technologies, the electrical constraints are becoming more stringent and consequently, the process of manual fix-up of electrical violations is becoming even more tedious.